This invention relates in general to binary scaled current sources and more particularly to such a source utilizing current switching. In a common approach to n-bit digital to analog (D/A) converters, a current source provides a set of dc currents of magnitude I.sub.k =2.sup.k-1 *I.sub.1 for k=1 to n, where I.sub.1 is the magnitude of the least significant current provided by the source. In response to an input binary number, a control section of the D/A converter directs to the output of the D/A converter selected ones of the currents I.sub.k. In general, the current I.sub.k is directed to the converter output if and only if the kth least significant bit of the binary number is a one. The sum of all of these currents directed to converter output is therefore proportional to the binary number.
In actual practice, the ratio between successive I.sub.k is not exactly 2 because there are small errors in the I.sub.k. Each of these errors should be small compared to the least significant current I.sub.1 so that the output current is generated to n-bits accuracy. As the number of bits of precision increases, the difficulty of producing correspondingly precise I.sub.k becomes increasingly difficult. In one type of binary scaled current source, the I.sub.k are generated by an R-2R ladder as shown in FIG. 13. The precision of each of the I.sub.k is determined by the precision of the resistance values of the elements in the R-2R ladder and by the uniformity of the voltage on the right hand side terminals of all 2R resistors. For D/A converters of resolution greater than 10 bits, precisely matched resistors are produced in a monolithic form of reasonable chip-area only with the use of expensive laser trimming or selective Zener diode shorting techniques after fabrication.
In a technique illustrated in FIG. 14 and presented by R. J. Van de Plassche in the article "Dynamic Element Matching for High Accuracy Monolithic D/A Converters", IEEE JSSC, pp. 795-800, vol. Sc-11, no.6, December 1976, the precision required for components of the current source is relieved somewhat by use of current switches that interleave currents to average out errors caused by imperfect matching of components. In that approach, a current of magnitude 2I is supplied to a first divider that is to produce two currents each of magnitude I. However, because of mismatch between components of the first divider, a first one of the currents has magnitude (1+e)*I and the second of the currents has magnitude (1-e)*I, where e is a measure of the error in the two resulting currents. These two currents are supplied to a first switch which is responsive to a clock having a 50% duty cycle. During the first half of a clock cycle, the first current is directed to an output a and the second of the currents is directed to an output b. In the other half of the clock cycle, the first current is directed to output b and the second current is directed to output a. If the duty cycle were exactly 50%, then the average current I.sub.a at output a and the average current I.sub.b at output b would each equal I.
In general, the duty cycle is 50% plus some fractional error f (i.e., the duty cycle is 0.5*(1+f)) so that the current I.sub.a is equal to (1+ef)*I and I.sub.b is equal to (1-ef)*I. Because the error is now ef instead of e, the precision of the components in the first switch and divider can be relaxed somewhat without reduction in the precision of I.sub.a and I.sub.b. A series of dividers and switches can be cascaded as in FIG. 14 to produce a set of binary scaled output currents for use in a D/A converter. Although this technique reduces somewhat the precision required for elements, the scheme is still inherently limited by such precision as well as the precision of the duty cycle. It would therefore be advantageous to have a new type of source of binary scaled currents that is not so limited.